Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format.
For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp` command. For synthesis, the compiler generates netlists in the desired format.
The compiler proper is intended to elaborate and parse design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form.
This is a fairly large and complex standard, so it will take some time for it to get there, but that`s the goal.
NOTE: Icarus Verilog is a work in progress, and since the language standard is not standing still either, it probably always will be.
What`s New in This Release: [ read full changelog ]
Language Coverage Edit:
· Add support for using the &&, || and?
